• Single 3.3V (± 0.3V) power supply
• High speed clock cycle time -6: 166MHz<3-3-3>, -7H: 133MHz<2-2-2>, -7: 133MHz<3-3-3>, -8: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks contorlled by BA0 & BA1 (Bank Select)
• Byte control by LDQM and UDQM for IC42S16800
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command
• Package 400mil 54-pin TSOP-2
DESCRIPTION
The IC42S81600 and IC42S16800 are high-speed 134,217,728-bit synchronous dynamic randomaccess memories, organized as 4,194,304 x 8 x 4 and 2,097,152 x 16 x 4 (word x bit x bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOP-2..
Datasheet
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